Data processing systems have generally been developed which utilize microcode architecture in which macroinstructions are suitably decoded so as to provide access to a microinstruction or to a sequence of microinstructions obtained from a suitable data store thereof. In order to reduce the data storage space required for the microinstructions and to avoid handling a large number of "wide" instruction words, certain microcode systems have utilized "two-level" microcode storage techniques. Such two-level configurations are based on the recognition that control information in the microinstruction words are often common to a large number of microinstructions. Therefore in order to avoid the repetitive storage of the same relatively large number of data bits required to store all of the control and sequencing information for each microinstruction separately, certain control information, which is common to many microinstructions, is stored in one store, e.g., a read-only-memory (ROM), separately from other control sequencing information which is stored in a different ROM store. At the first level of operation the control and sequencing process is performed with reference to a first microcode control store ROM (a "first" or "vertical" microcode level) to produce sequencing information as well as control information for use at a second level of operation, with reference to a second control microcode store ROM (a "second" or "horizontal" level) so as to provide a "horizontal" microinstruction which is decoded to generate the control signals required to perform the particular microcode operation involved, the control information in the horizontal microinstruction in many cases being common to many microinstructions.
A system utilizing such two-level microcode architecture is described in U.S. Pat. No. 4,371,925, issued on Feb. 1, 1983 to R. A. Carberry et al. Such a system is described as using a central processor unit having a horizontal control store ROM which stores control information common to many microinstructions and a separate vertical store ROM, together with sequencer control circuitry, which stores sequencing and execution control information. Each horizontal microinstruction represents a basic function to be performed, although one or more fields thereof may be subject to modification by one or more modifier fields supplied by the vertical store ROM, as part of the execution control information as described therein.
In such system only a single horizontal microinstruction control ROM and a single vertical microinstruction control ROM are required, the modified or unmodified horizontal microinstructions then being appropriately decoded by suitable horizontal decode logic to produce the required control signals for use by various units, e.g. an arithmetic logic unit (ALU), within the central processor unit for performing the desired operations represented by the particular microinstruction which is decoded.
In some systems it is desirable to utilize not only an arithmetic logic unit (ALU) for executing fixed point arithmetic operations but also to include in the overall system a separate arithmetic unit for executing floating point arithmetic operations (FPU unit). Normally each execution unit (ALU or FPU) requires its own microinstructions for performing whatever operations are executed thereby and, accordingly, when using a two-level microcode architecture, separate vertical and horizontal control ROMs are utilized for each of the arithmetic units. In order to improve the efficiency thereof a single microsequencer unit can be utilized to provide vertical information, e.g., horizontal control store ROM addresses for each of the ALU and FPU horizontal control store ROMs. Normally the microsequencer must supply the desired horizontal modifiers and addresses to the ALU and FPU units in sequence (i.e., non-simultaneously) so that each of the ALU or FPU operations can be performed separately in an appropriately designated sequence.
It is desirable, however, that both the ALU and FPU units be capable of operating simultaneously so that fixed point arithmetic operations and floating point arithmetic operations can be carried on in parallel, i.e., simultaneously.